\section{Experiment Results}\label{sec:experiment}

In this section, the results from cost-driven design optimization are shown. We implement the framework in C++ and use 45nm technology node. The gate size and wire pitches information are extracted from NanGate FreePDK45 Generic Open Cell Library~\cite{library}. The parameters used in the experiments are listed in Table~\ref{tab:parameter}. During the design optimization process, the area utilization variation is within the range of 20\% to keep the design practical. 
The cost related parameters in this experiment are from IC cost model~\cite{ICcostmodel}. We use 300mm TSMC dual gate CMOS logic process technology for device layer and 300mm UMC interposer process technology for interposer layer. TSV-based 3D bonding method is face-to-back bonding and die-to-wafer stacking.

\begin{table}\footnotesize
\caption{Parameters used in the experiments}
\vspace{-15pt}
\label{tab:parameter}
\begin{center}
\begin{tabular}{l|l}
\hline
Parameter & Value \\ \hline \hline
Average gates per block & 50 \\ \hline
Average gate fanout & 2 \\ \hline
Rent's coefficient (k) & 4 \\ \hline
Rent's exponent (p) & 0.7 \\ \hline
TSV area & $1\mu m^2$ \\ \hline
Default area utilization & 70\% \\ \hline
Routing efficiency & 10\% \\ \hline
\end{tabular}
\vspace{-15pt}
\end{center}
\end{table}

%\subsection{Metal Layer Estimation}
%Metal layer estimation plays an important role in our cost efficient design exploration flow. The estimated metal layers have impact on cost in the following ways: (i) metal layers influence the process steps and masks number, resulting in different fabrication cost; (ii) metal layers have impact on the chip area by changing the routing demand.
%
%We vary the routing efficiency to exam how the available routing area influence required metals. In the experiment setting, the initial routing efficiency is 10\%. When we increase the routing efficiency to 20\%, the required metal layers reduces significantly. Designs with 50M gate counts need 5 meta layers when the routing efficiency is 10\%, but only 3 metal layers are needed after the efficiency increased. It is because for lower metal layers, the wire pitches are smaller, within the same available routing area, more interconnects can be accommodated with lower metal layers. When we increase the routing efficiency, the routing capacity of lower metal layers increased and the area occupied by vias of higher metal layers is reduced. Increasing the routing efficiency has great impact on required metal layers, however, the routing efficiency is determined after detailed placement when the net terminal locations and power/ground distribution networks are known \cite{kahng01}. In our exploration flow, the routing efficiency is set as constant.

\subsection{Cost Analysis without Optimization}
The costs of 2D designs, TSV-based and interposer-based designs with default area utilization and minimum required metal layers are calculated. All the 3D designs are partitioned into 2 layers, although the framework is capable to support 3D designs with more tiers. The cost comparison without optimization are shown in Figure~\ref{fig:comp1}.

\begin{figure}
\centering
\includegraphics[width=0.45\textwidth]{figures/implecom.pdf}
\caption{Cost comparison between design implementation on 2D, 2 tiers 3D TSV-based, and interposer-based 3D designs.}
\vspace{-15pt}
\label{fig:comp1}
\end{figure}

The fabrication cost rises with increased gate count as expected. When the gate count is smaller than 100M, the 2D implementation has lower cost than corresponding 3D cases. However, as the gate count continuously increased, 3D designs show the advantages of smaller footprint and less routing complexity over 2D designs. In the proposed flow, we only consider one interposer layer design, and the interposer area is determined by the maximum tier size. When the gate count increased, the cost of interposer is higher than 3D TSV bonding due to the lower die yield and higher wafer cost of larger interposer area. In previous work~\cite{xiangyu2010}, the gate count of 3D enabling point is less than 100M, which is smaller than our results because the previous process technology is 65nm. As transistor size continuously scaling, the chip size is reduced, and therefore amortized cost per chip is lower, making 3D stacking designs more cost-efficient for larger designs.
 
Besides 2 tiers partitioning, 3D TSV-based design costs with more tiers are examined. The costs are shown in Figure~\ref{fig:comp2}. In 3D TSV-based designs, more tiers do not necessarily lead to higher fabrication cost. From the results, for larger designs with gate count more than 150M, we can gain cost saving by partitioning the design into more tiers. It is because when the design is large, the TSV bonding cost overhead is compensated by smaller footprint since the die yield is exponentially related to the chip size.

\begin{figure}
\centering
\includegraphics[width=0.45\textwidth]{figures/layercom.pdf}
\caption{Fabrication costs of 2, 3, and 4 tiers TSV-based 3D designs; 2D and interposer-based design costs are shown for comparison.}
\vspace{-15pt}
\label{fig:comp2}
\end{figure}

\subsection{Cost Analysis with optimization}

In this section, the results after cost-efficient optimization are shown. For each design (both 2D and 3D cases), the optimal utilization and maximum utilization are obtained to calculate the corresponding design costs. The results are shown in Table~\ref{tab:results} with the most cost efficient utilization.

\begin{table*}\footnotesize
\caption{Results of optimal designs after cost-driven optimization process for 2D, TSV and interposer based 3D designs}
\vspace{-15pt}
\label{tab:results}
\begin{center}
\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|}\hline
\hline
{\bf{Gate Count}} &\multicolumn{3}{|c|}{\bf{2D Design}} & \multicolumn{4}{|c|}{\bf{TSV-based 3D}} & \multicolumn{3}{|c|}{\bf{interposer-based 3D}} \\ \cline{2-11}
 & metal layer & area util (\%) & cost & tier num & metal layers & area util (\%) & cost & metal layer & area util(\%) & cost\\ \hline
5M & 3 & 89 & 7.17 & 2 & 3 & 89 & 17.06 & 3 & 89 & 16.51 \\ \hline
10M & 3 & 81 & 8.18 & 2 & 3 & 89 & 17.93 & 3 & 89 & 17.44\\ \hline
50M & 5 & 79 & 18.34 & 2 & 4 & 79 & 27.26 & 4 & 79 & 27.47\\ \hline
100M &6 & 78 & 38.81 & 2 & 5 & 79 & 41.88 & 5 & 79 & 43.18  \\ \hline
150M & 6 & 72 & 78.37 & 2 & 5 & 73 & 65.72 & 5 & 73 & 68.77\\ \hline
200M & 7 & 71 & 131.85 & 3 & 5 & 75 & 87.97 & 6 & 78 & 89.45\\ \hline
250M & 8 & 70 & 204.62 & 4 & 5 & 76 & 111.52 & 6 & 75 & 127.01 \\ \hline
\end{tabular}
\end{center}
\end{table*}

%Column 2 shows the required metal layers under default area utilization for each design. For small designs with 5M or 10M gate counts, 3 metal layers are enough for signal routing. The estimated metal layers based on the routing model introduced in Section \ref{sec:model} are optimistic. Current process technologies usually provide 9 to 11 metal layers for a complex design. However, the metal layer estimation is closely related to the routable chip area and routing efficiency, which is determined by the detailed design. At the early stage, the detailed information of design is unknown, thus the metal layer estimation only depends on the model estimation.
Among all the designs, the most cost-efficient designs are obtained when the area utilization rate is higher than the default utilization, implying the significant impact of chip area on fabrication cost. In 2D designs, the optimal utilization decreases when the gate counts increases. The optimal utilization is achieved when all the metal layers are fully utilized for signal routing. For small designs, the top metal layer is usually with low utilization, only a small portion of interconnects is used. The large designs with higher gate counts require more routing resources causing high utilization even in high metal layers. It makes the large designs harder to shrink the chip area. In this results, 89\% chip area utilization is the optimal utilization for 5M gate count designs, but for designs with 150M gate counts, the optimal utilization decreases to 72\%.

After the design optimization, the costs of 2D and 3D designs are significantly reduced. Cost savings are shown in Table~\ref{tab:saving}. 2D designs have the highest saving on average except the last design when the original design before optimization is already the best one. TSV and interposer based designs have significant cost saving after the optimization. For large designs, the benefits are higher because of larger flexibility in chip area.

\begin{table*}[htbp]\footnotesize
\caption{Cost Savings of 2D, TSV and interposer based 3D designs for optimal area utilization with default metal layers}
\vspace{-15pt}
\label{tab:saving}
\begin{center}
\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|} \hline
\hline
Gate Count & \multicolumn{2}{|c|}{50M} & \multicolumn{2}{|c|}{100M} & \multicolumn{2}{|c|}{150M} & \multicolumn{2}{|c|}{200M} & \multicolumn{2}{|c|}{250M} \\ \hline
2D Savings & 5.34 & 22.54\% & 17.09 & 30.58\% & 25.83 & 24.79\% & 48.53 & 26.9\% & 0 & 0\%\\ \hline
3D TSV & 3.86 & 12.41\% & 11.04 & 20.87\% & 15.06 & 18.65\% & 21.48 & 19.62\% & 27.52 & 19.79\%\\ \hline
3D Interposer & 3.96 & 12.59\% & 11.25 & 20.68\% & 15.03 & 17.94\% & 33.65 & 28.50\% & 45.82 & 26.51\% \\ \hline
\end{tabular}
\vspace{-15pt}
\end{center}
\end{table*}

Although chip area reduction is the major factor for cost saving, metal layer reduction also provides cost saving compared to the baseline designs. Only one metal layer is reduced in the experiment because significant area overhead is introduced after aggressive metal layer reduction resulting in high fabrication cost. The cost saving results from metal layer reduction is shown Table~\ref{tab:metalreduction}. In order to maintain feasible routing after one metal layer reduction, chip area is increased to provide additional routing resources. The area increment percentage depends on different designs. For example, designs with low utilized top metal layer can have metal layer reduction with very small area overhead. But for some designs, area needs to increase about 10\% to enable one metal layer reduction, thus the cost saving is negative since cost overhead for larger chip area overweighs the cost saving from metal layer reduction. For 2D designs with 200M gate counts, when the area increases only 1\%, the required metal layer can be reduced. Thus the cost saving for the design is high. For 3 layer 3D TSV designs with 50M gate counts, in order to gain one metal layer reduction, the area needs to increase 20\%, so no cost saving can be achieved from metal layer reduction. On average, the area increment is within 10\% for designs to have one metal layer reduced in 2D and 3D cases.

\begin{table}[htbp]\footnotesize
\caption{Cost Savings of 2D, TSV-based, and interposer-based 3D designs with metal layer reduction technique}
\vspace{-15pt}
\label{tab:metalreduction}
\begin{center}
\begin{tabular}{|c|c|c|c|c|c|} \hline
\hline
Gate Count & 50M & 100M & 150M & 200M & 250M \\ \hline
2D Savings & 3.01 & 10.19 & 6.04 & 38.57 & -11.78\\ \hline
2 layer 3D TSV & -8.46 & 6.11 & 3.08 & 20.73 & 21.09 \\ \hline
3 layer 3D TSV & -4.11 & 0.98 & 9.28 & 7.83 & 2.69 \\ \hline
4 layer 3D TSV & -3.85 & 3.16 & 0.46 & 12.51 & 11.62 \\ \hline
3D Interposer & 1.43 & 5.94 & 2.16 & 20.18 & 19.68\\ \hline
\end{tabular}
\vspace{-15pt}
\end{center}
\end{table} 